Method for synchronizing signals and structures therefor
US5818890A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1996 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Sep 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0338
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A serial data signal is synchronized to a clock signal in a synchronization circuit (10). Synchronization is accomplished by generating a plurality of delayed versions of the serial data signal using serially connected delay elements (21-27). The delayed versions of the serial data signal are sampled using a set of flip-flops (11-18). The sampled delayed data signals appearing at the outputs of each flip-flop of the set of flip-flops (11-18) are used to determine which delayed data signal is most closely aligned to the clock signal. The output of the multiplexer (40) is an aligned serial data signal. In addition, a drift correction circuit (50) continuously monitors and corrects the alignment between the clock signal and the aligned serial data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.