Computer system bus performance monitoring
US5819053A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1996 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Jun 5, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3495
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Performance of a bus in a computer system is monitored. A predetermined total period is counted, and usage of the bus for data transfers during the total period is measured. The bus is monitored for active cycles and a period is counted in which the active cycles are present during the total period. The bus is monitored for data transfer cycles and a period is counted in which the data transfer cycles are present during the total period. Bus efficiency is measured based on the active period and data transfer period. Read data usage on the bus is also measured. A first amount of data read by a first device is monitored, and a second amount of read data used by a second bus device is monitored. The read efficiency is determined based on the first and second amounts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.