Interrupption recovery and resynchronization of events in a computer
US5819114A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 15, 1996 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Aug 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4843
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system employs systems and methods that are transparent to the operating system and application programs, for interruption recovery and resynchronization of events including a playback FIFO buffer having an underrun counter that counts the number of audio samples that could not be read from the playback FIFO buffer because the playback FIFO buffer was empty. When the playback FIFO buffer goes empty, an interrupt is asserted to signal the processor to read the underrun counter to determine how many samples it missed and to advance its pointers forward to "re-sync" the data stream. The computer system further preferably includes a capture FIFO buffer to capture samples from an ADC and having an overrun counter that counts the number of audio samples that could not be written to the capture FIFO buffer because the capture FIFO buffer was full. The capture FIFO buffer generates an interrupt to signal the processor to read the overrun counter to determine how many samples it missed and to fill a record buffer with a number of samples equal to the overrun count, wherein each sample has a predetermined value preferably equal to the value of the last input before overrun.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.