Dual vertical thermal processing furnace
US5820366A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Aug 23, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67778
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A vertical semiconductor wafer processing furnace that includes a single housing having first and second vertical furnaces each having a heating chamber for heat treating a semiconductor wafer. The first and second vertical furnaces are asymmetrically disposed relative to each other to reduce the overall footprint of the processing furnace. Each vertical furnace includes a wafer support assembly that includes support structure, such as a wafer boat, boat elevator, motor and guide rod, for axially mounting a selected number of semiconductor wafers. A translation element selectively moves one of the support elements along the vertical axis into and out of the process tube, and a wafer transfer element selectively transfers semiconductor wafers to or from one of the support elements. The furnace further includes a heating sleeve or envelope that is adapted to control the ambient fluid environment surrounding the support structure and which is independently movable relative to support structure. The heating sleeve is adapted to sealingly engage a portion of the support element to create a fluid-tight seal forming a loadlock processing assembly. This assembly is coupled to a vertical tr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.