Methods of forming hemispherical grained silicon electrodes including multiple temperature steps
US5821152A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Oct 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/712
Abstract
A method of forming a hemispherical grained silicon electrode includes the steps of forming an amorphous silicon layer on an integrated circuit substrate, and heating the integrated circuit substrate and the amorphous silicon layer to a first deposition temperature. The amorphous silicon layer is exposed to a source gas including silicon while maintaining the first deposition temperature thereby forming silicon crystal nuclei on a surface of the amorphous silicon layer. The temperature of the integrated circuit substrate is lowered to a second deposition temperature wherein the second deposition temperature is less than the first deposition temperature. The silicon crystal nuclei are exposed to the source gas including silicon while maintaining the second deposition temperature thereby increasing a size of the silicon crystal nuclei. The silicon layer and the silicon crystal nuclei are then annealed thereby further increasing the size of the silicon crystal nuclei to provide hemispherical grains on the silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.