Semicoductor device having a hetero interface with a lowered barrier
US5821555A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Mar 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/01335
Abstract
A semiconductor device includes a first semiconductor layer formed of first semiconductor, a second semiconductor layer formed on the first semiconductor layer and formed of second semiconductor of a group different from a group to which the first semiconductor belongs, and a third semiconductor layer formed between the first and second semiconductor layers, the third semiconductor layer being one of a layer formed of third semiconductor of the same group as the first semiconductor and having an impurity concentration higher than the first semiconductor layer and a layer formed of fourth semiconductor of the same group as the second semiconductor and having an impurity concentration higher than the second semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.