Surface mount package with low coefficient of thermal expansion
US5821617A · kind A · utility
14Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Jul 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A surface mount package for use with large area silicon device. The package uses a pressed ceramic frame and solid metal pads which are closely matched for coefficient of thermal expansion (CTE) to each other and to the silicon die. The package is specifically designed for large area die (greater than 0.0625 inches squared) and for high temperature eutectic alloy bonding. All materials of the package are CTE matched to each other and to silicon within 10%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.