Method and apparatus to interface monotonic and non-monotonic domino logic
US5821775A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Dec 27, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01855
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is an improved interface between monotonic and non-monotonic domino logic. A monotonic domino logic block is clocked by CLK. The last stage of the monotonic domino logic is clocked by the delayed clock, DCLK, to extend its evaluation period beyond Phase I by a brief window of time, t.sub.d. The true output and the inverted output of the last stage of the monotonic domino logic block are inputs to a non-monotonic domino evaluation tree. The non-monotonic domino evaluation tree operates while an evaluation control block is ON. The evaluation control block is ON only during that extension of the evaluation period, t.sub.d, for a time less than or equal to the period t.sub.d. Since the output of the last stage of the monotonic logic block remains stable during this extended evaluation period, and the non-monotonic domino evaluation tree operates at most during this window of time, there is no need to use latches or use a dual rail implementation for the monotonic logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.