Circuitry for providing a high impedance state when powering down a single port node
US5821796A · kind A · utility
37Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Sep 23, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network circuit has a single port device 28 having a high impedance output node 42 when the single port device 28 is powered down; and a multi port device 50 having a bias node 60 coupled to the output node 42.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.