CMOS high-speed differential to single-ended converter circuit
US5821809A · kind A · utility
53Cited by
20References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | May 23, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45658
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS differential to single-ended converter is implemented. A differential input stage comprised of a pair of N-channel transistors draws current through two fixed current P-channel load transistors. A first N-channel differential transistor provides negative feedback bias control of a current source transistor coupled to the differential input stage. The negative feedback control provides increased current gain in the second N-channel transistor, which drives a CMOS inverter to a full rail-to-rail voltage swing on its output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.