Method for using built in self test to characterize input-to-output delay time of embedded cores and other integrated circuits
US5822228A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 27, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | May 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for using a BIST generator and a BIST compactor to characterize the propagation delay time of a high-speed embedded cores and integrated circuits in general. In one embodiment, an external clock is provided having a positive edge and a negative edge. The BIST generator and test compactor is configured to apply a set of test inputs to the integrated circuit in response to the positive edge, and the BIST compactor is configured to latch a set of outputs from the integrated circuit in response to the negative edge, and determine if the set of outputs represent a valid test result. The validity determination is monitored, and as long as the test result is valid, it is determined that the propagation delay time is less than the time interval between the positive and negative transitions. The propagation delay time can then be measured by reducing the time interval until invalid test results appear. This method provides the means to measure propagation delays of embedded cores more accurately using since tester pulse widths are more accurately measured than tester channel to channel accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.