Method of writing data to a single transistor type ferroelectric memory
US5822239A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Jul 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is directed to a writing method to effectively suppress inter-cell interference when writing data to a single transistor type ferroelectric memory. When V is a writing voltage, stripe-like conducting electrodes are row electrodes, and semiconductor stripes are column electrodes, then the writing method includes a first procedure and a successive second procedure based on V/3 rule. In the first procedure, when a voltage of +V is applied to the row electrode of the cell being observed, while a voltage of zero is applied to the column electrode, and voltages of +V/3 are applied to the other row electrodes, and voltages of +(2/3)V are applied to the other column electrodes, then in the second procedure, a voltage of zero is applied to the row electrode of the cell being observed, while a voltage of +V/3 is applied to the column electrode, and voltages of +V/3 are applied to the other row electrodes, and voltages of zero are applied to the other column electrodes. In the first procedure, when a voltage of -V is applied to the row electrode of the cell being observed, while a voltage of zero is applied to the column electrode, and voltages of -V/3 are applied to the other r…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.