Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers
US5822251A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Sep 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash-memory system is expandable. Rather than directly connecting individual flash-memory chips to a controller, flash buffer chips are used. Each flash buffer chip can connect to four banks of flash-memory chips. Chip enables for individual chips in a bank are generated from an address sent to the flash buffer chips. Two flash-specific DMA controllers are provided, each with four DMA state machines for controlling the four banks of flash-memory chips attached to a flash buffer chip. This allows for four-way interleaving. Two flash buses connect the two DMA controllers to flash buffer chips. The flash bus has a narrow byte-wide interface to send command, address, and data bytes from the DMA controller to the flash buffer chips. These command, address, and data bytes are then passed through the flash buffer chip to the flash-memory chips. Two additional command signals on the flash bus are used to select and control the flash buffer chips. Busy signals from all flash-memory chips in a bank are connected together, and the four busy signals from the four banks are time-multiplexed to a single common busy line for the flash bus. The four DMA state machines each monitor one period of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.