Semiconductor memory device capable of relieving fixed-failure memory cells and refresh-failure memory cells
US5822257A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 6, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | May 6, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device has a plurality of word lines, a plurality of bit lines crossing the word lines, and a memory cell array having memory cells disposed at respective points of intersection between the word lines and the bit lines. The memory device includes a first redundant memory cell array, a first address comparison circuit, a second redundant memory cell array, and a second address comparison circuit. The first redundant memory cell array replaces memory cells with redundant memory cells per bit or a small number of bits. The first address comparison circuit stores an addresses of memory cells to be replaced, compares the stored addresses with an inputted address, and allows a memory cell to be replaced effectively with a redundant memory cell in the first redundant memory cell array when a stored address matches the inputted address. The second redundant memory cell array replaces memory cells with redundant memory cells per word line or bit line. The second address comparison circuit stores addresses corresponding to word lines or bit lines to be replaced, compares the stored addresses with an inputted address, and allows memory cells to be replaced effectively with redundant …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.