Apparatus for fast phase-locked loop (PLL) frequency slewing during power on
US5822387A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Mar 25, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock synthesizer is disclosed that includes a phase-locked loop circuit having two modes of operation: a non-slewing mode of operation, and a frequency-slewing mode of operation. During the power-up of the system, the PLL is controlled to operate in the non-slewing mode of operation to effect rapid variations in the output frequency. A power-on reset circuit is disclosed which determines when the system is in the power-up interval, and generates a power-on-reset signal to so indicate. The PLL operates in a frequency-slewing mode after power-up to provide controlled transitions in the frequency of the output reference signal of the PLL. A phase-locked loop circuit having structure to implement both modes is provided, as well as an adjustable lock detector circuit. The output of the lock detector, a logical lock signal, is used to enable the frequency-slewing mode of the PLL circuit. During power-up, the power-on-reset signal is deasserted, and disables the lock detector from generating the frequency-slewing mode enable signal. The PLL thus operates in a non-slewing mode during power-up. After the power-on-reset signal has been asserted, the lock detector is permitted to generate …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.