Passive backplane capable of being configured to a variable data path width corresponding to a data size of the pluggable CPU board
US5822551A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Jun 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/14
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a first passive backplane having a local bus, a memory bus, and peripheral bus. The computer system includes a first printed circuit board having a microprocessor, and connected to the local bus and to the memory bus. The computer system includes a second printed circuit board having a memory and connected to the memory bus. The computer system also includes a third printed circuit board having a peripheral controller, and connected to the local bus and to the peripheral bus The disclosed computer system further includes a second backplane. The second backplane is connected to the first passive backplane through a connector, where at least one of the local and peripheral buses extends from the first passive backplane to the second backplane through the connector. The computer system also includes a plurality of peripheral slots located on the second backplane and connected to the peripheral bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.