Multiple parallel digital data stream channel controller architecture
US5822553A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Mar 13, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/122
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple data stream channel controller providing demand driven transport of multiple data streams concurrently in real time through a peripheral data channel coupled between a general purpose processor system and a special purpose processor system. The controller comprises a first bus master interface coupleable to a general purpose processor system bus, a second bus master interface coupleable to a special purpose processor system bus, a segmentable buffer memory and a controller that directs the transfer of data segments between the first and second bus master interfaces via the segmentable buffer memory. The controller is responsive to a plurality of signals provided by the special purpose processor bus to request transfer of successive data segments from a respective plurality of data streams staged in the segmentable buffer memory. The controller moderates the transfer of successive data segments of the respective plurality of data streams via the first bus master interface to the segmentable buffer memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.