Controlling power up using clock gating
US5822596A · kind A · utility
17Cited by
9References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1995 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Nov 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.