Microprocessor-based data processing apparatus that commences a next overlapping cycle when a ready signal is detected not to be active
US5822779A · kind A · utility
33Cited by
15References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Mar 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/786
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing technique with which a CPU core accesses memory devices over a bus. Some of the memory devices are on-chip, and some may be off-chip. In order to optimize its operation, the CPU core accesses the on-chip devices via a core buffer interface unit ("BIU") which has been tuned to on-chip operation. Off-chip devices communicate with the CPU core via a system BIU which translates the on-chip bus transactions to meet the off-chip device requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.