Mechanism for prefetching targets of memory de-reference operations in a high-performance processor
US5822788A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Dec 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system provides enhanced performance when executing irregular code that include pointer de-reference operations. A memory controller of the computer system first fetches a pointer value from an address location in the memory and then calculates a new address adding a constant or scale factor to the pointer value. A logical-to-physical (i.e., virtual-to-physical) translation of the pointer value is also performed. The loading of data for the initial pointer load operation is overlapped with the de-reference operation, wherein the de-reference data is prefetched from memory using the resulting address and placed into the CPU's cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.