Method of manufacturing a semiconductor device with BICMOS circuit
US5824560A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Mar 27, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/009
Abstract
A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is to be used for the bipolar transistor and a second region for the MOS transistor. The two regions are provided in that order with a gate dielectric layer (10) and an auxiliary layer (11) of non-crystalline silicon. The auxiliary layer and the gate dielectric layer are subsequently removed from the first region. Then an electrode layer (13) of non-crystalline silicon is deposited. An emitter electrode (15) is formed in the electrode layer on the first region, and a gate electrode (16) is formed both in the electrode layer and in the auxiliary layer on the second region. The electrode layer is subjected to a treatment whereby non-crystalline silicon is removed and whereby a layer of non-crystalline silicon is formed on the surface of the silicon body which has substantially the same thickness at the area of the first region and at the area of the second region. Over…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.