Semiconductor device including a nonvolatile memory
US5825062A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Dec 10, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/687
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Pulse shaped voltage of 5V is applied to a source region 3 at initial phase of erase by a pull back voltage generator 13 connected to the sources region 3. Then, the pulse shaped voltages of 10V and 12V increased under stepwise bases are applied to source region 3 with progress of erasion. Generation of hot-holes at the initial phase of data erasion can be prevented because difference in voltage between the floating gate electrode 5 and source region 3 is decreased. Value of the pulse shaped voltage thus applied is increased for the difference occurred between the floating gate electrode 5 and source region 3 when erasion is in much progress. Thus, it is possible to pull out the stored electrons from the floating gate electrode 5 until the threshold voltages can be set at predetermined values. So that, degradation of characteristics of a gate oxidation layer caused by hot-holes generated with erasion can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.