Variable logic integrated circuit device having connections through switch matrix and top layers for inter-cell connections
US5825203A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Nov 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable logic integrated circuit device formed on a semiconductor chip comprising variable logic blocks and switch matrices laid out alternately in the X and Y directions in a checkerboard pattern. Above the variable logic blocks is a block interconnection wiring arrangement formed by multiple-layer wiring techniques. The variable logic blocks and switch matrices are wired into circuits respectively by a lower wiring layer in the multiple wiring layer setup of the chip. The block interconnection wiring is formed by an upper wiring layer extending above the variable logic blocks and included in the multiple wiring layer setup. The switch matrices are used to connect the block interconnection lines to one another as well as to the variable logic blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.