Amplifier-less low power switched-capacitor techniques
US5825230A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1997 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Aug 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/331
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switched-capacitor gain-boost network includes a bank of N-substantially identical sampling capacitors connectable to an output node. An integrating capacitor has one node connected to a low potential node and a second node connected to the output node. The integrating capacitor is connected to the bank of sampling capacitors in parallel when the bank of sampling capacitors is connected to the output node. Sampling period switches are actuable during a sampling period to connect the sampling capacitors of the bank in parallel and to connect the bank between an analog signal input node and a low potential node to charge the sampling capacitors. Integrating period switches are actuable during an integrating period to connect the sampling capacitors of the bank in series and to connect the bank between a low potential node and the output node to dump the charge stored by the sampling capacitors onto the integrating capacitor. A method of providing dc gain to an analog input signal is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.