Digital-to-analog converter and method of calibrating
US5825317A · kind A · utility
56Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1997 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Apr 7, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/742
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A ferroelectric transistor (72) is programmed with a gate voltage that shifts a threshold voltage of the ferroelectric transistor (72). The shifted threshold voltage generates a correction current (.DELTA.I.sub.(N-1)) in a combination circuit (52) that trims an output voltage of a DAC trim circuit (50). A ferroelectric material (32) of the ferroelectric transistor (72) stores a charge in accordance with a programming voltage and allows a dynamic adjustment of the correction current (.DELTA.I.sub.(N-1)) that is used to modify the output voltage of the DAC trim circuit (50).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.