Image processing system including a variable size memory bus
US5825372A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1994 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Jun 29, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system incorporates a processor that includes a data bus having a fixed N-bits size connected to an n-bits word memory through a bus having an n-bits size, where N is a multiple of n, and n is a variable value. The system includes means for, at each execution by the processor of a write instruction of one word of N bits in the memory, successively writing each sub-word of n bits constituting this word of N bits at distinct addresses, and means for, at each execution of a read instruction of a word of N bits in the memory, successively reading in this memory at distinct addresses sub-words of n bits, and juxtaposing these sub-words on the fixed size bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.