Divider/multiplier circuit having high precision mode
US5825681A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Jan 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5354
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A divider/multiplier circuit (10) is disclosed. In a divider mode, numerator terms are coupled to a normalizer (14) which generates normalized numerator values and corresponding numerator exponent values therefrom. Denominator terms are coupled to a look-up normalizer (20) which generates normalized denominator inverse values and corresponding denominator exponent values therefrom. The numerator and denominator exponent values are summed in an adder circuit (18) to generate a sum exponent value. The normalized numerator and inverse denominator values are multiplied in a multiplier circuit (16) to generate a normalized quotient value. The normalized quotient value is denormalized according to the sum exponent value. In a multiply mode of operation first and second multiplicands are coupled to the multiplier circuit (16). In a high precision divide mode, a sequence of numerator and inverse denominator values are coupled to the multiplier circuit (16) to generate a sequence of partial product terms. The partial product terms are accumulated in a high precision loop (24) to provide a high precision division value. Negative multiplicands and numerator values are handled by a leading abs…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.