Dual port memory device and a method therefor
US5825713A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 8, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Feb 8, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual port memory device and method for outputting serial data at a high speed from a memory array through a data register. The device includes a RAM port and a SAM port. The SAM port receives start column address data from the RAM port during a transfer cycle and the data register is filled with row data from a specified row. During this process, the start column address is latched and incremented, then the incremented address loaded into a serial counter as an initial address to set up a pipeline serial output. After completion of the transfer cycle, the serial counter is controlled by a serial clock and causes column data to be prefetched from the data register and supplied to an output buffer for serial output. Because of the pipeline configuration, data is serially output at a high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.