Compressed Instruction format for use in a VLIW processor
US5826054A · kind A · utility
45Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | May 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.