Having write merge and data override capability for a superscalar processing device
US5826069A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1993 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Sep 27, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism and method for use in a superscalar microprocessor for storing into a register file within a single clock cycle, the results of multiple instructions (or micro-ops) that become available for storage into the register file at the same instant thus avoiding a microprocessor stall. The present invention may store, during a single clock cycle, results of up to four instructions that become available at the same time and that may target the same register, flag or portion thereof. By storing the results of the instructions (that are executed in parallel) at the same time, the present invention avoids inefficient stalls otherwise associated with prior art microprocessors when to or more instructions (or micro-ops) target the same register, register portion, or flag. The present invention utilizes a special decoder scheme, coupled with merge and priority logic to store the results into the real register file within a single clock cycle. Results of multiple instructions that may target the same register or the same register portion (i.e., data prioritizations are required) or results that target different portions of the same register (i.e., data merges are required) are supplie…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.