Method and apparatus for performance optimization in power-managed computer systems
US5826092A · kind A · utility
67Cited by
22References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 15, 1995 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Sep 15, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The performance of a computer system which use reduction of clock speed to conserve power is enhanced by dynamically adjusting the minimum number of clock cycles required for memory access ("wait states"). When the computer system decreases its clock speed, the minimum number of wait states is decreased to account for the longer cycle time. Likewise, when the computer system increases its clock speed, this invention determines whether any increase in the minimum number of wait states is required, and if so, implements such an increase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.