Radio frequency noise reduction arrangement
US5826181A · kind A · utility
15Cited by
4References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 10, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Oct 10, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/08
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A frequency selective noise reduction circuit and finds application in receiver demodulator arrangements in mobile telecommunication base stations. A receive signal is divided into two paths. One path includes a Phase Lock Loop circuit (PLL) which is employed to identify noise. The noise signal is inverted and then combined with the other signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.