Use of early formed lift-off layer in fabricating gated electron-emitting devices
US5827099A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1995 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Dec 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2201/319
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.