Array of thin film transistors without a step region at intersection of gate bus and source bus electrodes
US5828083A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 19, 1996 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Mar 19, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array of thin film transistors, which minimizes a stepped part in a cross-over region between a gate bus line and a source bus line. Each thin film transistor in the array has associated therewith a structure which includes: a gate bus electrode located on a substrate surface, a first insulating layer covering the gate bus electrode and the substrate surface, a non-monocrystalline semiconductor layer on the first insulating layer above the gate bus electrode, a second insulating layer on the non-monocrystalline semiconductor layer above the gate bus electrode, an n+ monocrystalline layer on the second insulating layer and the non-monocrystalline layer, and a source bus electrode on the n+ monocrystalline layer. A bus line structure in the array is fabricated by the process described above. In the bus line structure, each of the non-monocrystalline semiconductor layer, the second insulating layer, and the n+ non-monocrystalline semiconductor layer is patterned in the same direction as the source bus line. Additionally, the second insulating film is made wider than the source bus line and both the non-monocrystalline semiconductor layer and the n+ non-monocrystalline semiconductor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.