ESD tolerated SOI device
US5828106A · kind A · utility
16Cited by
5References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1997 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Aug 20, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
Abstract
A semiconductor-on-insulator (SOI) type semiconductor device with an enhanced electrostatic discharge (ESD) tolerance having a semiconductor layer on an insulating support substrate, comprising a pair of voltage supply lines formed on the semiconductor layer, a pair of low resistivity semiconductor regions connected to said pair of source supplying lines and disposed within the layer, and a dielectric region disposed between said pair of low resistivity semiconductor regions; wherein said pair of low resistivity semiconductor regions form a capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.