Semi-conductor integrated circuit device
US5828109A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1997 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Mar 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
Abstract
In a semi-conductor integrated circuit device, electric charges which relate to latch-up phenomenon generation are absorbed effectively, and thereby generation of the latch-up phenomenon is prevented. Low-concentration impurity diffusion layers of I/O transistor within I/O transistor region are electrically connected to high-concentration impurity diffusion layers with different conductive characteristics each. Furthermore, low-concentration impurity diffusion layers of internal circuit transistors within internal circuit transistor region are electrically connected to high-concentration impurity diffusion layers with different conductive characteristics each, or are brought into directly contact therewith, thus electrically connecting thereto. For this reason, it causes an observed area of the low-concentration impurity diffusion layer of the transistors to enlarge, thus absorbing the electric charges causing the latch-up phenomenon generation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.