Pulsed reset single phase domino logic
US5828234A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 1996 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Aug 27, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The pulsed reset single phase dynamic logic of the present invention reorders the conventional modes of operation such that in a single cycle of operation of a domino logic circuit, reset occurs first, followed sequentially by gap2, evaluation and gap1. To reset each domino stage prior to evaluating, a reset pulse is propagated to each domino stage, with an evaluate signal arriving at each stage as the reset pulse is ending. The circuit configuration of the present invention creates a different, but shorter and easier to manage set of race conditions. The present invention permits the creation of faster and more robust circuit designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.