Phase locked loop having adaptive jitter reduction
US5828255A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1996 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Nov 15, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Jitter is controlled in a phase locked loop (PLL) adaptively and continuously in real time by a jitter control circuit. The jitter control circuit makes periodic PLL output jitter measurements and causes sequential measurements to be compared. The comparison provides an indication as to whether output jitter is being improved or degraded. Charge pump gains associated with internal parameters and external parameters that adversely affect output jitter are modified in response to the comparisons. If output jitter is adversely affected by an increment or decrement of one of the gain values, then the gain value is moved in the opposite direction. Output jitter is optimized for both gain values. Such optimization occurs during normal circuit operation and is continuous so as to adapt to changing conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.