Output buffer circuit
US5828260A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 1996 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | May 16, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A detecting penetration current causing logic part (12a) gives, when the logic is H level at both nodes (N15, N24), the logical product thereof H to a condition adding part (12b) as an activated detection signal. In the condition adding part (12b), it is confirmed that the activation of the detection signal is longer than a specified time, by a delay circuit (G21) and NAND gate (G22). Consequently, logic H is given to a forced logic presenting part (12c). In the forced logic presenting part (12c), NMOS transistors (Q13, Q14) are turned on, and logic L is given by force to both nodes (N15, N24) to get out of a state where a current would flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.