Degenerated differential pair with controllable transconductance
US5828265A · kind A · utility
21Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 1997 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | May 8, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G1/0029
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential pair with input transistors and provided with a variable degeneration resistor. The degeneration resistor comprises a series arrangement of two branches of coupled resistors which are shunted in mutually corresponding points by respective control transistors whose gates are interconnected. The differential pair further comprises a control loop comprising two current mirrors a bias resistor and a current source for providing a control signal to the gates of the control transistors. The control loop does not influence the DC bias of the differential pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.