High speed dynamic range extension employing a synchronous digital detector
US5828328A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 1996 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Jun 28, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/188
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An high speed apparatus and method for extending a dynamic range of a signal processing device which receives an analog input signal. A peak indicator uses a 90.degree. phase shifter and zero crossing detector to indicate when the analog input signal is at a peak amplitude within each of its cycles, and an analog to digital converter (ADC) samples input signal amplitude when each peak amplitude is indicated to provide a digital control word for each sampled peak. A gain controller adjusts the gain of the analog input signal provided to the signal processing device in response to the digital word. Preferably the ADC calculates log.sub.2 of the sampled peak amplitude so that the digital word is a power-of-two operator, the gain controller compresses the analog input signal by a factor of one over the power-of-two, and the output signal from the signal processing device is thereafter expanded by a data shifter which shifts the output by an amount corresponding to the power-of-two.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.