Multi level power converter with self-correcting capacitor charge timing adjustment
US5828561A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1996 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Aug 16, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/4837
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multilevel converter comprising, in particular, a capacitor (C1, C2, . . . , Cn) in each of its cells. The capacitors nominally have charge voltages proportional to their respective ranks in the converter. The converter also includes circuits (VMO1, VMO2, . . . , VMOn) for evaluating the mean voltage across the terminals of each of the capacitors (C1, C2, . . . , Cn), circuits (VE1, VE2, . . . , VEn) for measuring any difference that may occur with respect to each of the capacitors (C1, C2, . . . , Cn) between the evaluated mean charge voltage and the nominal mean charge voltage of the capacitor, and for providing a corresponding difference signal (VEC1, VEC2, . . . , VECn), and also correction control circuits (BT, EC1, EC2, . . . , ECn) receiving the difference signals and correspondingly causing at least one temporary coupling to be established between two capacitors in order to correct the difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.