Method and circuit for controlling a precharge cycle of a memory device
US5828612A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1997 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Oct 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for optimally controlling memory array bit line precharge timing to increase memory frequency of operation by generating a precharge output (110) for memory array bit lines in response to the earliest asserted control input among precharge control inputs. A write precharge signal (218) early enables a write precharge operation by enabling the precharge signal (110) a delayed period after an enabling falling dock edge of clock (104), as indicated by a write precharge enable signal (210), and during a write cycle, as indicated by a write precharge trigger (212). Thereafter, a default precharge trigger (216) is enabled to ensure that write precharging operation continues for an extended and optimal duration. A read precharge trigger (214) enables precharging after a read operation by enabling the precharge signal (110) in close proximity to the disabling of read sense amplifiers within the memory array to enhance post-read precharging. Thereafter, the default precharge trigger (216), is enabled to ensure that the read precharging operation continues for an extended and optimal duration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.