Integrated network switch having mixed mode switching with selectable full frame/half frame switching
US5828664A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 18, 1997 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Feb 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13405
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An integrated network switch operable in either full-frame or half-frame switching modes on a circuit-by-circuit basis. To effect selective operation in either full-frame or half-frame switching modes, an information memory buffer has the capacity of storing two samples per port. A connection memory contains the source addresses for the output ports. The most significant bit of an address designates the first or second sample of the two sample information memory buffer. For half-frame mode operation, the current value of the most significant bit of the write pointer (the address being written to) is used in the source address for reading when the source address is less than the write pointer. However, when the source address is greater than the write pointer, the most significant bit position is switched. For full-frame mode operation, the most significant bit of the source address will always take the inverse of the most significant bit for the write pointer. This assures that the read frame is always in the half of the two sample buffer not then being written to.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.