Memory system with multiplexed input-output port and systems and methods using the same
US5829016A · kind A · utility
7Cited by
9References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1996 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Apr 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1678
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory including a plurality of input/output terminals 220 for exchanging data bits during a data access cycle and receiving command and control bits during a command and control cycle. The memory further includes an array of memory cells 201, a data input/output circuitry for transferring data between the input/output terminals and the array of memory cells during the data access cycle, and control circuitry for controlling operations of the memory in response to command and control bits received at the input/output terminals during the command and control cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.