System and method for preventing stale data in multiple processor computer systems
US5829035A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1997 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Oct 3, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99952
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor computer system comprising a data storage device, a memory controller, and a plurality of processors. The data storage device has a plurality of memory lines, each memory line having a portion for alternatively storing data or, a set of GONE codes, a count value, and a processor identification code value. A memory controller coupled to the data storage alternatively stores and retrieves data or the GONE code, the count field value and the processor identification code value. At least one of the processors includes a cache memory and a cache memory controller. The cache memory controller compares a GONE code associated with the requested memory line with the contents of the requested memory line, and requests the contents of the requested memory line from a second of the processors in response to the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.