Semiconductor device soldering process
US5830781A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1997 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Apr 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A pair of metal lead frames are stacked together with a plurality of solder coated semiconductor chips sandwiched between respective pairs of overlapped portions of the lead frames and the lead frame stack is then disposed within a fixture comprising spaced apart clamping means for clamping together the overlapped portions of the lead frames. Only the clamping means contact the frame stack and in thermally and electrically insulated relation therewith for minimizing heat loss from and electrical shorting of the lead frame stack to the fixture. Electrodes are tightly clamped against exposed ends of the lead stack for passing electrical current through the stack for causing electrical resistance heating of the stack and the soldering of the chips to the lead frames.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.