Resistless methods of gate formation in MOS devices
US5830801A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1997 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Jan 2, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28052
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an MOS gate includes providing a silicon substrate having a gate oxide formed thereon, forming a polysilicon layer on the gate oxide, defining a gate area including forming an oxide mask by positioning a light mask adjacent a surface of the polysilicon layer and exposing the surface through the light mask to a deep ultra violet light in an ambient containing oxygen. A layer of metal is deposited and annealed to form a silicide only where the layer of metal and polysilicon layer are in contact. The remaining metal layer and mask are removed, using the silicide as a mask, wherein the remaining polysilicon and the silicide form an MOS gate. Sidewall spacers are formed on opposing sides of the MOS gate and used in forming self aligned source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.