Semiconductor static random access memory device

US5831285A · kind A · utility

Assignee

• SEIKO EPSON CORPORATION · JP

Inventors

• Masahiro Takeuchi · Tokyo, JP
• Yasunobu Tokuda · Suwa, JP

Key dates

• Filing date: Jan 17, 1996
• Grant date: Nov 3, 1998
• Expiry date: Jan 17, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/15

Abstract

A first word line connects the gate electrodes of first transfer transistors in adjacent memory cells. A second word line connects the gate electrodes of second transfer transistors in adjacent memory cells. A ground line connects the source regions of first and second driver transistors. The first and second word lines and ground line are formed by a wiring layer different from the wiring layer that forms the gate electrodes of the first and second transfer transistors. The ground line shields the first and second driver transistors, TFTs and the like. Drain contacts include chamfered sides between which the ground line is disposed.