Trench storage dram cell including a step transfer device
US5831301A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1998 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Jan 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.